1. Field of the Invention
The invention relates to a decoding method for a memory-based Viterbi decoder and, more particularly, to a decoding method for a Viterbi decoder that applies the mechanisms of path matching and path prediction.
2. Description of the Related Art
Error correction codes have been playing a key role in data transmission because adding them into digitalized data ensures the correctness of data during data transmission. In general, error correction codes can be classified into two categories. One category is a block code, which employs a method to encode data per block, there being no time relation between each block. The other category is a convolutional code, which, unlike the block code, has a time relation existing in the encoding process.
The most common method applied to a convolutional code decoder is the Viterbi algorithm, which is also the most effective decoding algorithm for the convolutional code. A decoder that employs such algorithm is called a Viterbi decoder. During the decoding process, the existing architecture must decode a certain length of data, regardless of whether the data is correct or incorrect, in order to obtain correct data. That certain length of data is referred to as a truncation length. During decoding, a large amount of memory bandwidth is necessary due to the large number of memory access operations required. Typically, however, decoding a smaller amount of data than that of the truncation length is sufficient for judging the precision of data. For this reason, a lot of power is wasted during memory access.
U.S. Pat. No. 5,208,816 illustrates the redundant power consumption. This prior art system provides a memory algorithm for a high-speed Viterbi decoder, which transmits a parity checking code for inspecting the Viterbi decoder and determining data reliability. When unreliable data has been detected, a second round of Viterbi estimation or retransmission will be executed to increase data precision. The method of U.S. Pat. No. 5,208,816 is only suitable for low-speed transmission. Moreover, because a conventional Viterbi decoder is used, which requires a lot of memory bandwidth, low power consumption is difficult to achieve.
Another reference, U.S. Pat. No. 4,905,317, discloses a system which synthesizes the states when executing the path trace-back operation in such a manner as to implement a jumping back effect so that memory access operations can be decreased as well as decoding speed being increased. Unfortunately, even though the decoding speed has been increased, it cannot satisfy the current demand for decoding speed when applied. Additionally, the paths that have been traced back by jumping back must be retraced at the next decoding step, because the data in these paths are likely to be a solution required for subsequently decoded data. This retracing requires many redundant calculations and memory read operations.
The present invention provides a method for a memory-based Viterbi decoder, which employs mechanisms for path matching and path prediction to reduce the number of memory access operations and the power consumption so that the aforementioned shortcomings of the prior art can be overcome.